Expand description
Control 2 Register
Modules§
- CLK_SEL
- Clock Source Select
- DBGEN
- Debug Enable
- FORCE
- Force Initialization
- FORCE_
SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
- FRCEN
- FRCEN
- INDEP
- Independent or Complementary Pair Operation
- INIT_
SEL - Initialization Control Select
- PWM23_
INIT - PWM23 Initial Value
- PWM45_
INIT - PWM45 Initial Value
- PWMX_
INIT - PWM_X Initial Value
- RELOAD_
SEL - Reload Source Select
- WAITEN
- WAIT Enable