Expand description
DCDC Register 3
Modules§
- DISABLE_
STEP - Disable stepping for the output VDD_SOC of DCDC
- MINPWR_
DC_ HALFCLK - Set DCDC clock to half freqeuncy for continuous mode
- MISC_
DELAY_ TIMING - Ajust delay to reduce ground noise
- MISC_
DISABLEFET_ LOGIC - Reserved
- TARGET_
LP - Target value of standby (low power) mode 0x0: 0
- TRG
- Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V