Module REG0

DCDC Register 0

Modules

ADJ_POSLIMIT_BUCK

adjust value to poslimit_buck register

CURRENT_ALERT_RESET

reset current alert signal

CUR_SNS_THRSH

Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert

DISABLE_AUTO_CLK_SWITCH

Disable automatic clock switch from internal osc to xtal clock.

EN_LP_OVERLOAD_SNS

enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically

LP_HIGH_HYS

Adjust hysteretic value in low power from 12.5mV to 25mV

LP_OVERLOAD_FREQ_SEL

the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle

LP_OVERLOAD_THRSH

the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode

OVERCUR_TRIG_ADJ

The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0

PWD_CMP_BATT_DET

set to “1” to power down the low voltage detection comparator

PWD_CMP_OFFSET

power down output range comparator

PWD_CUR_SNS_CMP

The power down signal of the current detector.

PWD_HIGH_VOLT_DET

power down overvoltage detection comparator

PWD_OSC_INT

Power down internal osc. Only set this bit, when 24 MHz crystal osc is available

PWD_OVERCUR_DET

power down overcurrent detection comparator

PWD_ZCD

power down the zero cross detection function for discontinuous conductor mode

SEL_CLK

select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set.

STS_DC_OK

Status register to indicate DCDC status. 1’b1: DCDC already settled 1’b0: DCDC is settling

XTALOK_DISABLE

1’b1: Disable xtalok detection circuit 1’b0: Enable xtalok detection circuit

XTAL_24M_OK

set to 1 to switch internal ring osc to xtal 24M