#[repr(u8)]pub enum SPEED_A {
STANDARD = 1,
FAST = 2,
HIGH = 3,
}
Expand description
These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.
1: standard mode (100 kbit/s)
2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
3: high speed mode (3.4 Mbit/s)
Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
Value on reset: 2
Variants§
STANDARD = 1
1: Standard Speed mode of operation
FAST = 2
2: Fast or Fast Plus mode of operation
HIGH = 3
3: High Speed mode of operation