Type Alias rp2040_pac::xip_ctrl::ctrl::W

pub type W = W<CTRL_SPEC>;

Register CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn en(&mut self) -> EN_W<'_, CTRL_SPEC>

Bit 0 - When 1, enable the cache. When the cache is disabled, all XIP accesses
will go straight to the flash, without querying the cache. When enabled,
cacheable XIP accesses will query the cache, and the flash will
not be accessed if the tag matches and the valid bit is set.

If the cache is enabled, cache-as-SRAM accesses have no effect on the
cache data RAM, and will produce a bus error response.

pub fn err_badwrite(&mut self) -> ERR_BADWRITE_W<'_, CTRL_SPEC>

Bit 1 - When 1, writes to any alias other than 0x0 (caching, allocating)
will produce a bus fault. When 0, these writes are silently ignored.
In either case, writes to the 0x0 alias will deallocate on tag match,
as usual.

pub fn power_down(&mut self) -> POWER_DOWN_W<'_, CTRL_SPEC>

Bit 3 - When 1, the cache memories are powered down. They retain state,
but can not be accessed. This reduces static power dissipation.
Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot
be enabled when powered down.
Cache-as-SRAM accesses will produce a bus error response when
the cache is powered down.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual