Struct rp2040_pac::xip_ctrl::ctr_acc::CTR_ACC_SPEC

pub struct CTR_ACC_SPEC;

Cache Access counter
A 32 bit saturating counter that increments upon each XIP access,
whether the cache is hit or not. This includes noncacheable accesses.
Write any value to clear.

You can read this register and get ctr_acc::R. You can reset, write, write_with_zero this register using ctr_acc::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for CTR_ACC_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CTR_ACC_SPEC

reset() method sets CTR_ACC to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CTR_ACC_SPEC

write(|w| ..) method takes ctr_acc::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for CTR_ACC_SPEC

read() method returns ctr_acc::R reader structure