Type Alias rp2040_pac::spi0::sspcr1::W

pub type W = W<SSPCR1_SPEC>;

Register SSPCR1 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn lbm(&mut self) -> LBM_W<'_, SSPCR1_SPEC>

Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.

pub fn sse(&mut self) -> SSE_W<'_, SSPCR1_SPEC>

Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.

pub fn ms(&mut self) -> MS_W<'_, SSPCR1_SPEC>

Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.

pub fn sod(&mut self) -> SOD_W<'_, SSPCR1_SPEC>

Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual