Struct rp2040_pac::sio::fifo_st::FIFO_ST_SPEC

pub struct FIFO_ST_SPEC;

Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.

You can read this register and get fifo_st::R. You can reset, write, write_with_zero this register using fifo_st::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for FIFO_ST_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for FIFO_ST_SPEC

reset() method sets FIFO_ST to value 0x02

const RESET_VALUE: u32 = 2u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for FIFO_ST_SPEC

write(|w| ..) method takes fifo_st::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 12u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for FIFO_ST_SPEC

read() method returns fifo_st::R reader structure