Struct rp2040_pac::sio::interp0_accum1_add::INTERP0_ACCUM1_ADD_SPEC

pub struct INTERP0_ACCUM1_ADD_SPEC;

Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).

You can read this register and get interp0_accum1_add::R. You can reset, write, write_with_zero this register using interp0_accum1_add::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for INTERP0_ACCUM1_ADD_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for INTERP0_ACCUM1_ADD_SPEC

reset() method sets INTERP0_ACCUM1_ADD to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for INTERP0_ACCUM1_ADD_SPEC

write(|w| ..) method takes interp0_accum1_add::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for INTERP0_ACCUM1_ADD_SPEC

read() method returns interp0_accum1_add::R reader structure