Struct rp2040_pac::pll_sys::fbdiv_int::FBDIV_INT_SPEC

pub struct FBDIV_INT_SPEC;

Feedback divisor
(note: this PLL does not support fractional division)

You can read this register and get fbdiv_int::R. You can reset, write, write_with_zero this register using fbdiv_int::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for FBDIV_INT_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for FBDIV_INT_SPEC

reset() method sets FBDIV_INT to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for FBDIV_INT_SPEC

write(|w| ..) method takes fbdiv_int::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for FBDIV_INT_SPEC

read() method returns fbdiv_int::R reader structure