Type Alias rp2040_pac::pio0::sm::sm_execctrl::R

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pub type R = R<SM_EXECCTRL_SPEC>;
Expand description

Register SM_EXECCTRL reader

Aliased Type§

struct R { /* private fields */ }

Implementations§

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impl R

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pub fn status_n(&self) -> STATUS_N_R

Bits 0:3 - Comparison level for the MOV x, STATUS instruction

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pub fn status_sel(&self) -> STATUS_SEL_R

Bit 4 - Comparison used for the MOV x, STATUS instruction.

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pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R

Bits 7:11 - After reaching wrap_top, execution is wrapped to this address.

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pub fn wrap_top(&self) -> WRAP_TOP_R

Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom.
If the instruction is a jump, and the jump condition is true, the jump takes priority.

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pub fn out_sticky(&self) -> OUT_STICKY_R

Bit 17 - Continuously assert the most recent OUT/SET to the pins

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pub fn inline_out_en(&self) -> INLINE_OUT_EN_R

Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable
When used in conjunction with OUT_STICKY, writes with an enable of 0 will
deassert the latest pin write. This can create useful masking/override behaviour
due to the priority ordering of state machine pin writes (SM0 < SM1 < …)

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pub fn out_en_sel(&self) -> OUT_EN_SEL_R

Bits 19:23 - Which data bit to use for inline OUT enable

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pub fn jmp_pin(&self) -> JMP_PIN_R

Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.

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pub fn side_pindir(&self) -> SIDE_PINDIR_R

Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values

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pub fn side_en(&self) -> SIDE_EN_R

Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.

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pub fn exec_stalled(&self) -> EXEC_STALLED_R

Bit 31 - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.