Struct rp2040_pac::pio0::irq_force::IRQ_FORCE_SPEC

pub struct IRQ_FORCE_SPEC;

Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.

You can reset, write, write_with_zero this register using irq_force::W. See API.

Trait Implementations

impl RegisterSpec for IRQ_FORCE_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for IRQ_FORCE_SPEC

reset() method sets IRQ_FORCE to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for IRQ_FORCE_SPEC

write(|w| ..) method takes irq_force::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1