Type Alias rp2040_pac::i2c0::ic_con::W

pub type W = W<IC_CON_SPEC>;

Register IC_CON writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn master_mode(&mut self) -> MASTER_MODE_W<'_, IC_CON_SPEC>

Bit 0 - This bit controls whether the DW_apb_i2c master is enabled.

NOTE: Software should ensure that if this bit is written with ‘1’ then bit 6 should also be written with a ‘1’.

pub fn speed(&mut self) -> SPEED_W<'_, IC_CON_SPEC>

Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.

This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.

1: standard mode (100 kbit/s)

2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)

3: high speed mode (3.4 Mbit/s)

Note: This field is not applicable when IC_ULTRA_FAST_MODE=1

pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W<'_, IC_CON_SPEC>

Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.

pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W<'_, IC_CON_SPEC>

Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing

pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W<'_, IC_CON_SPEC>

Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.

Reset value: ENABLED

pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W<'_, IC_CON_SPEC>

Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.

If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.

NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.

pub fn stop_det_ifaddressed( &mut self, ) -> STOP_DET_IFADDRESSED_W<'_, IC_CON_SPEC>

Bit 7 - In slave mode: - 1’b1: issues the STOP_DET interrupt only when it is addressed. - 1’b0: issues the STOP_DET irrespective of whether it’s addressed or not. Reset value: 0x0

NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1’b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).

pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W<'_, IC_CON_SPEC>

Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.

Reset value: 0x0.

pub fn rx_fifo_full_hld_ctrl( &mut self, ) -> RX_FIFO_FULL_HLD_CTRL_W<'_, IC_CON_SPEC>

Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.

Reset value: 0x0.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual