The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
You can read
this register and get timer0::R
. You can reset
, write
, write_with_zero
this register using timer0::W
. You can also modify
this register. See API.
For information about available fields see timer0
module
struct TIMER0 { /* private fields */ }