Struct rp2040_pac::dma::RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Expand description

Register block

Implementations§

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impl RegisterBlock

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pub const fn ch(&self, n: usize) -> &CH

0x00..0x300 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG

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pub fn ch_iter(&self) -> impl Iterator<Item = &CH>

Iterator for array of: 0x00..0x300 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG

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pub const fn intr(&self) -> &INTR

0x400 - Interrupt Status (raw)

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pub const fn inte0(&self) -> &INTE0

0x404 - Interrupt Enables for IRQ 0

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pub const fn intf0(&self) -> &INTF0

0x408 - Force Interrupts

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pub const fn ints0(&self) -> &INTS0

0x40c - Interrupt Status for IRQ 0

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pub const fn inte1(&self) -> &INTE1

0x414 - Interrupt Enables for IRQ 1

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pub const fn intf1(&self) -> &INTF1

0x418 - Force Interrupts for IRQ 1

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pub const fn ints1(&self) -> &INTS1

0x41c - Interrupt Status (masked) for IRQ 1

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pub const fn timer0(&self) -> &TIMER0

0x420 - Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

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pub const fn timer1(&self) -> &TIMER1

0x424 - Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

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pub const fn timer2(&self) -> &TIMER2

0x428 - Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

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pub const fn timer3(&self) -> &TIMER3

0x42c - Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

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pub const fn multi_chan_trigger(&self) -> &MULTI_CHAN_TRIGGER

0x430 - Trigger one or more channels simultaneously

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pub const fn sniff_ctrl(&self) -> &SNIFF_CTRL

0x434 - Sniffer Control

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pub const fn sniff_data(&self) -> &SNIFF_DATA

0x438 - Data accumulator for sniff hardware
Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.

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pub const fn fifo_levels(&self) -> &FIFO_LEVELS

0x440 - Debug RAF, WAF, TDF levels

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pub const fn chan_abort(&self) -> &CHAN_ABORT

0x444 - Abort an in-progress transfer sequence on one or more channels

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pub const fn n_channels(&self) -> &N_CHANNELS

0x448 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.

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pub const fn ch0_dbg_ctdreq(&self) -> &CH0_DBG_CTDREQ

0x800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch0_dbg_tcr(&self) -> &CH0_DBG_TCR

0x804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch1_dbg_ctdreq(&self) -> &CH1_DBG_CTDREQ

0x840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch1_dbg_tcr(&self) -> &CH1_DBG_TCR

0x844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch2_dbg_ctdreq(&self) -> &CH2_DBG_CTDREQ

0x880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch2_dbg_tcr(&self) -> &CH2_DBG_TCR

0x884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch3_dbg_ctdreq(&self) -> &CH3_DBG_CTDREQ

0x8c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch3_dbg_tcr(&self) -> &CH3_DBG_TCR

0x8c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch4_dbg_ctdreq(&self) -> &CH4_DBG_CTDREQ

0x900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch4_dbg_tcr(&self) -> &CH4_DBG_TCR

0x904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch5_dbg_ctdreq(&self) -> &CH5_DBG_CTDREQ

0x940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch5_dbg_tcr(&self) -> &CH5_DBG_TCR

0x944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch6_dbg_ctdreq(&self) -> &CH6_DBG_CTDREQ

0x980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch6_dbg_tcr(&self) -> &CH6_DBG_TCR

0x984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch7_dbg_ctdreq(&self) -> &CH7_DBG_CTDREQ

0x9c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch7_dbg_tcr(&self) -> &CH7_DBG_TCR

0x9c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch8_dbg_ctdreq(&self) -> &CH8_DBG_CTDREQ

0xa00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch8_dbg_tcr(&self) -> &CH8_DBG_TCR

0xa04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch9_dbg_ctdreq(&self) -> &CH9_DBG_CTDREQ

0xa40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch9_dbg_tcr(&self) -> &CH9_DBG_TCR

0xa44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch10_dbg_ctdreq(&self) -> &CH10_DBG_CTDREQ

0xa80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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pub const fn ch10_dbg_tcr(&self) -> &CH10_DBG_TCR

0xa84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer

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pub const fn ch11_dbg_ctdreq(&self) -> &CH11_DBG_CTDREQ

0xac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.

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