Type Alias rp2040_pac::dma::intr::W

pub type W = W<INTR_SPEC>;

Register INTR writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn intr(&mut self) -> INTR_W<'_, INTR_SPEC>

Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.

Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.

This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.

It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual