Struct rp2040_pac::clocks::clk_peri_selected::CLK_PERI_SELECTED_SPEC

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pub struct CLK_PERI_SELECTED_SPEC;
Expand description

Indicates which SRC is currently selected by the glitchless mux (one-hot).
This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

You can read this register and get clk_peri_selected::R. See API.

Trait Implementations§

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impl RegisterSpec for CLK_PERI_SELECTED_SPEC

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type Ux = u32

Raw register type (u8, u16, u32, …).
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impl Resettable for CLK_PERI_SELECTED_SPEC

reset() method sets CLK_PERI_SELECTED to value 0x01

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const RESET_VALUE: u32 = 1u32

Reset value of the register.
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fn reset_value() -> Self::Ux

Reset value of the register.
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impl Readable for CLK_PERI_SELECTED_SPEC

read() method returns clk_peri_selected::R reader structure

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