Struct imxrt_ral::trng::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 31 fields
    pub MCTL: RWRegister<u32>,
    pub SCMISC: RWRegister<u32>,
    pub PKRRNG: RWRegister<u32>,
    pub PKRMAX: RWRegister<u32>,
    pub SDCTL: RWRegister<u32>,
    pub SBLIM: RWRegister<u32>,
    pub FRQMIN: RWRegister<u32>,
    pub FRQMAX: RWRegister<u32>,
    pub SCML: RWRegister<u32>,
    pub SCR1L: RWRegister<u32>,
    pub SCR2L: RWRegister<u32>,
    pub SCR3L: RWRegister<u32>,
    pub SCR4L: RWRegister<u32>,
    pub SCR5L: RWRegister<u32>,
    pub SCR6PL: RWRegister<u32>,
    pub STATUS: RORegister<u32>,
    pub ENT: [RORegister<u32>; 16],
    pub PKRCNT10: RORegister<u32>,
    pub PKRCNT32: RORegister<u32>,
    pub PKRCNT54: RORegister<u32>,
    pub PKRCNT76: RORegister<u32>,
    pub PKRCNT98: RORegister<u32>,
    pub PKRCNTBA: RORegister<u32>,
    pub PKRCNTDC: RORegister<u32>,
    pub PKRCNTFE: RORegister<u32>,
    pub SEC_CFG: RWRegister<u32>,
    pub INT_CTRL: RWRegister<u32>,
    pub INT_MASK: RWRegister<u32>,
    pub INT_STATUS: RORegister<u32>,
    pub VID1: RORegister<u32>,
    pub VID2: RORegister<u32>,
    /* private fields */

}
Expand description

TRNG

Fields§

§MCTL: RWRegister<u32>

Miscellaneous Control Register

§SCMISC: RWRegister<u32>

Statistical Check Miscellaneous Register

§PKRRNG: RWRegister<u32>

Poker Range Register

§PKRMAX: RWRegister<u32>

Poker Maximum Limit Register

§SDCTL: RWRegister<u32>

Seed Control Register

§SBLIM: RWRegister<u32>

Sparse Bit Limit Register

§FRQMIN: RWRegister<u32>

Frequency Count Minimum Limit Register

§FRQMAX: RWRegister<u32>

Frequency Count Maximum Limit Register

§SCML: RWRegister<u32>

Statistical Check Monobit Limit Register

§SCR1L: RWRegister<u32>

Statistical Check Run Length 1 Limit Register

§SCR2L: RWRegister<u32>

Statistical Check Run Length 2 Limit Register

§SCR3L: RWRegister<u32>

Statistical Check Run Length 3 Limit Register

§SCR4L: RWRegister<u32>

Statistical Check Run Length 4 Limit Register

§SCR5L: RWRegister<u32>

Statistical Check Run Length 5 Limit Register

§SCR6PL: RWRegister<u32>

Statistical Check Run Length 6+ Limit Register

§STATUS: RORegister<u32>

Status Register

§ENT: [RORegister<u32>; 16]

Entropy Read Register

§PKRCNT10: RORegister<u32>

Statistical Check Poker Count 1 and 0 Register

§PKRCNT32: RORegister<u32>

Statistical Check Poker Count 3 and 2 Register

§PKRCNT54: RORegister<u32>

Statistical Check Poker Count 5 and 4 Register

§PKRCNT76: RORegister<u32>

Statistical Check Poker Count 7 and 6 Register

§PKRCNT98: RORegister<u32>

Statistical Check Poker Count 9 and 8 Register

§PKRCNTBA: RORegister<u32>

Statistical Check Poker Count B and A Register

§PKRCNTDC: RORegister<u32>

Statistical Check Poker Count D and C Register

§PKRCNTFE: RORegister<u32>

Statistical Check Poker Count F and E Register

§SEC_CFG: RWRegister<u32>

Security Configuration Register

§INT_CTRL: RWRegister<u32>

Interrupt Control Register

§INT_MASK: RWRegister<u32>

Mask Register

§INT_STATUS: RORegister<u32>

Interrupt Status Register

§VID1: RORegister<u32>

Version ID Register (MS)

§VID2: RORegister<u32>

Version ID Register (LS)

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