Expand description
SPDIFTxClk Register
Modules§
- SYSCLK_
DF - system clock divider factor, 2~512.
- TXCLK_
DF - Divider factor (1-128)
- TXCLK_
SOURCE - no description available
- TX_
ALL_ CLK_ EN - Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1.