Struct imxrt_ral::ocotp::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 54 fields
pub CTRL: RWRegister<u32>,
pub CTRL_SET: RWRegister<u32>,
pub CTRL_CLR: RWRegister<u32>,
pub CTRL_TOG: RWRegister<u32>,
pub TIMING: RWRegister<u32>,
pub DATA: RWRegister<u32>,
pub READ_CTRL: RWRegister<u32>,
pub READ_FUSE_DATA: RWRegister<u32>,
pub SW_STICKY: RWRegister<u32>,
pub SCS: RWRegister<u32>,
pub SCS_SET: RWRegister<u32>,
pub SCS_CLR: RWRegister<u32>,
pub SCS_TOG: RWRegister<u32>,
pub VERSION: RORegister<u32>,
pub TIMING2: RWRegister<u32>,
pub LOCK: RWRegister<u32>,
pub CFG0: RWRegister<u32>,
pub CFG1: RWRegister<u32>,
pub CFG2: RWRegister<u32>,
pub CFG3: RWRegister<u32>,
pub CFG4: RWRegister<u32>,
pub CFG5: RWRegister<u32>,
pub CFG6: RWRegister<u32>,
pub MEM0: RWRegister<u32>,
pub MEM1: RWRegister<u32>,
pub MEM2: RWRegister<u32>,
pub MEM3: RWRegister<u32>,
pub MEM4: RWRegister<u32>,
pub ANA0: RWRegister<u32>,
pub ANA1: RWRegister<u32>,
pub ANA2: RWRegister<u32>,
pub SRK0: RWRegister<u32>,
pub SRK1: RWRegister<u32>,
pub SRK2: RWRegister<u32>,
pub SRK3: RWRegister<u32>,
pub SRK4: RWRegister<u32>,
pub SRK5: RWRegister<u32>,
pub SRK6: RWRegister<u32>,
pub SRK7: RWRegister<u32>,
pub SJC_RESP0: RWRegister<u32>,
pub SJC_RESP1: RWRegister<u32>,
pub MAC0: RWRegister<u32>,
pub MAC1: RWRegister<u32>,
pub GP3: RWRegister<u32>,
pub GP1: RWRegister<u32>,
pub GP2: RWRegister<u32>,
pub SW_GP1: RWRegister<u32>,
pub SW_GP20: RWRegister<u32>,
pub SW_GP21: RWRegister<u32>,
pub SW_GP22: RWRegister<u32>,
pub SW_GP23: RWRegister<u32>,
pub MISC_CONF0: RWRegister<u32>,
pub MISC_CONF1: RWRegister<u32>,
pub SRK_REVOKE: RWRegister<u32>,
/* private fields */
}
Expand description
no description available
Fields§
§CTRL: RWRegister<u32>
OTP Controller Control Register
CTRL_SET: RWRegister<u32>
OTP Controller Control Register
CTRL_CLR: RWRegister<u32>
OTP Controller Control Register
CTRL_TOG: RWRegister<u32>
OTP Controller Control Register
TIMING: RWRegister<u32>
OTP Controller Timing Register
DATA: RWRegister<u32>
OTP Controller Write Data Register
READ_CTRL: RWRegister<u32>
OTP Controller Write Data Register
READ_FUSE_DATA: RWRegister<u32>
OTP Controller Read Data Register
SW_STICKY: RWRegister<u32>
Sticky bit Register
SCS: RWRegister<u32>
Software Controllable Signals Register
SCS_SET: RWRegister<u32>
Software Controllable Signals Register
SCS_CLR: RWRegister<u32>
Software Controllable Signals Register
SCS_TOG: RWRegister<u32>
Software Controllable Signals Register
VERSION: RORegister<u32>
OTP Controller Version Register
TIMING2: RWRegister<u32>
OTP Controller Timing Register 2
LOCK: RWRegister<u32>
Value of OTP Bank0 Word0 (Lock controls)
CFG0: RWRegister<u32>
Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.)
CFG1: RWRegister<u32>
Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.)
CFG2: RWRegister<u32>
Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.)
CFG3: RWRegister<u32>
Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.)
CFG4: RWRegister<u32>
Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.)
CFG5: RWRegister<u32>
Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.)
CFG6: RWRegister<u32>
Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.)
MEM0: RWRegister<u32>
Value of OTP Bank1 Word0 (Memory Related Info.)
MEM1: RWRegister<u32>
Value of OTP Bank1 Word1 (Memory Related Info.)
MEM2: RWRegister<u32>
Value of OTP Bank1 Word2 (Memory Related Info.)
MEM3: RWRegister<u32>
Value of OTP Bank1 Word3 (Memory Related Info.)
MEM4: RWRegister<u32>
Value of OTP Bank1 Word4 (Memory Related Info.)
ANA0: RWRegister<u32>
Value of OTP Bank1 Word5 (Analog Info.)
ANA1: RWRegister<u32>
Value of OTP Bank1 Word6 (Analog Info.)
ANA2: RWRegister<u32>
Value of OTP Bank1 Word7 (Analog Info.)
SRK0: RWRegister<u32>
Shadow Register for OTP Bank3 Word0 (SRK Hash)
SRK1: RWRegister<u32>
Shadow Register for OTP Bank3 Word1 (SRK Hash)
SRK2: RWRegister<u32>
Shadow Register for OTP Bank3 Word2 (SRK Hash)
SRK3: RWRegister<u32>
Shadow Register for OTP Bank3 Word3 (SRK Hash)
SRK4: RWRegister<u32>
Shadow Register for OTP Bank3 Word4 (SRK Hash)
SRK5: RWRegister<u32>
Shadow Register for OTP Bank3 Word5 (SRK Hash)
SRK6: RWRegister<u32>
Shadow Register for OTP Bank3 Word6 (SRK Hash)
SRK7: RWRegister<u32>
Shadow Register for OTP Bank3 Word7 (SRK Hash)
SJC_RESP0: RWRegister<u32>
Value of OTP Bank4 Word0 (Secure JTAG Response Field)
SJC_RESP1: RWRegister<u32>
Value of OTP Bank4 Word1 (Secure JTAG Response Field)
MAC0: RWRegister<u32>
Value of OTP Bank4 Word2 (MAC Address)
MAC1: RWRegister<u32>
Value of OTP Bank4 Word3 (MAC Address)
GP3: RWRegister<u32>
Value of OTP Bank4 Word4 (MAC Address)
GP1: RWRegister<u32>
Value of OTP Bank4 Word6 (General Purpose Customer Defined Info)
GP2: RWRegister<u32>
Value of OTP Bank4 Word7 (General Purpose Customer Defined Info)
SW_GP1: RWRegister<u32>
Value of OTP Bank5 Word0 (SW GP1)
SW_GP20: RWRegister<u32>
Value of OTP Bank5 Word1 (SW GP2)
SW_GP21: RWRegister<u32>
Value of OTP Bank5 Word2 (SW GP2)
SW_GP22: RWRegister<u32>
Value of OTP Bank5 Word3 (SW GP2)
SW_GP23: RWRegister<u32>
Value of OTP Bank5 Word4 (SW GP2)
MISC_CONF0: RWRegister<u32>
Value of OTP Bank5 Word5 (Misc Conf)
MISC_CONF1: RWRegister<u32>
Value of OTP Bank5 Word6 (Misc Conf)
SRK_REVOKE: RWRegister<u32>
Value of OTP Bank5 Word7 (SRK Revoke)