Struct imxrt_ral::iomuxc::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 133 fields
    pub SW_MUX_CTL_PAD_GPIO_AD_14: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_13: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_12: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_11: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_10: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_09: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_08: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_07: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_06: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_05: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_04: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_03: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_02: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_01: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_AD_00: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_14: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_13: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_12: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_11: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_10: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_09: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_08: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_07: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_06: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_05: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_04: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_03: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_02: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_01: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_SD_00: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_13: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_12: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_11: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_10: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_09: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_08: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_07: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_06: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_05: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_04: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_03: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_02: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_01: RWRegister<u32>,
    pub SW_MUX_CTL_PAD_GPIO_00: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_14: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_13: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_12: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_11: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_10: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_09: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_08: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_07: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_06: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_05: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_04: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_03: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_02: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_01: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_AD_00: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_14: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_13: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_12: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_11: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_10: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_09: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_08: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_07: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_06: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_05: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_04: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_03: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_02: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_01: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_SD_00: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_13: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_12: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_11: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_10: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_09: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_08: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_07: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_06: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_05: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_04: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_03: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_02: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_01: RWRegister<u32>,
    pub SW_PAD_CTL_PAD_GPIO_00: RWRegister<u32>,
    pub USB_OTG_ID_SELECT_INPUT: RWRegister<u32>,
    pub FLEXPWM1_PWMA_SELECT_INPUT_0: RWRegister<u32>,
    pub FLEXPWM1_PWMA_SELECT_INPUT_1: RWRegister<u32>,
    pub FLEXPWM1_PWMA_SELECT_INPUT_2: RWRegister<u32>,
    pub FLEXPWM1_PWMA_SELECT_INPUT_3: RWRegister<u32>,
    pub FLEXPWM1_PWMB_SELECT_INPUT_0: RWRegister<u32>,
    pub FLEXPWM1_PWMB_SELECT_INPUT_1: RWRegister<u32>,
    pub FLEXPWM1_PWMB_SELECT_INPUT_2: RWRegister<u32>,
    pub FLEXPWM1_PWMB_SELECT_INPUT_3: RWRegister<u32>,
    pub FLEXSPI_DQS_FA_SELECT_INPUT: RWRegister<u32>,
    pub FLEXSPI_DQS_FB_SELECT_INPUT: RWRegister<u32>,
    pub KPP_COL_SELECT_INPUT_0: RWRegister<u32>,
    pub KPP_COL_SELECT_INPUT_1: RWRegister<u32>,
    pub KPP_COL_SELECT_INPUT_2: RWRegister<u32>,
    pub KPP_COL_SELECT_INPUT_3: RWRegister<u32>,
    pub KPP_ROW_SELECT_INPUT_0: RWRegister<u32>,
    pub KPP_ROW_SELECT_INPUT_1: RWRegister<u32>,
    pub KPP_ROW_SELECT_INPUT_2: RWRegister<u32>,
    pub KPP_ROW_SELECT_INPUT_3: RWRegister<u32>,
    pub LPI2C1_HREQ_SELECT_INPUT: RWRegister<u32>,
    pub LPI2C1_SCL_SELECT_INPUT: RWRegister<u32>,
    pub LPI2C1_SDA_SELECT_INPUT: RWRegister<u32>,
    pub LPI2C2_SCL_SELECT_INPUT: RWRegister<u32>,
    pub LPI2C2_SDA_SELECT_INPUT: RWRegister<u32>,
    pub LPSPI1_PCS_SELECT_INPUT_0: RWRegister<u32>,
    pub LPSPI1_SCK_SELECT_INPUT: RWRegister<u32>,
    pub LPSPI1_SDI_SELECT_INPUT: RWRegister<u32>,
    pub LPSPI1_SDO_SELECT_INPUT: RWRegister<u32>,
    pub LPSPI2_PCS_SELECT_INPUT_0: RWRegister<u32>,
    pub LPSPI2_SCK_SELECT_INPUT: RWRegister<u32>,
    pub LPSPI2_SDI_SELECT_INPUT: RWRegister<u32>,
    pub LPSPI2_SDO_SELECT_INPUT: RWRegister<u32>,
    pub LPUART1_RXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART1_TXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART2_RXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART2_TXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART3_RXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART3_TXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART4_RXD_SELECT_INPUT: RWRegister<u32>,
    pub LPUART4_TXD_SELECT_INPUT: RWRegister<u32>,
    pub NMI_GLUE_NMI_SELECT_INPUT: RWRegister<u32>,
    pub SPDIF_IN1_SELECT_INPUT: RWRegister<u32>,
    pub SPDIF_TX_CLK2_SELECT_INPUT: RWRegister<u32>,
    pub USB_OTG_OC_SELECT_INPUT: RWRegister<u32>,
    pub XEV_GLUE_RXEV_SELECT_INPUT: RWRegister<u32>,
    /* private fields */
}

Expand description

IOMUXC

Fields§

§SW_MUX_CTL_PAD_GPIO_AD_14: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_13: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_12: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_11: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_10: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_09: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_08: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_07: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_06: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_05: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_04: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_03: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_02: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_01: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_AD_00: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_14: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_14 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_13: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_13 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_12: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_12 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_11: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_11 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_10: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_10 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_09: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_09 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_08: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_08 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_07: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_07 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_06: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_06 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_05: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_05 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_04: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_04 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_03: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_03 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_02: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_02 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_01: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_01 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_SD_00: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_SD_00 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_13: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_13 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_12: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_12 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_11: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_11 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_10: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_10 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_09: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_09 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_08: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_08 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_07: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_07 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_06: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_06 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_05: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_05 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_04: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_04 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_03: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_03 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_02: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_02 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_01: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_01 SW MUX Control Register

§SW_MUX_CTL_PAD_GPIO_00: RWRegister<u32>

SW_MUX_CTL_PAD_GPIO_00 SW MUX Control Register

§SW_PAD_CTL_PAD_GPIO_AD_14: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_13: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_12: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_11: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_10: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_09: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_08: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_07: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_06: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_05: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_04: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_03: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_02: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_01: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_AD_00: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_14: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_14 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_13: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_13 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_12: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_12 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_11: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_11 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_10: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_10 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_09: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_09 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_08: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_08 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_07: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_07 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_06: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_06 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_05: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_05 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_04: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_04 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_03: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_03 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_02: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_02 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_01: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_01 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_SD_00: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_SD_00 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_13: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_13 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_12: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_12 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_11: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_11 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_10: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_10 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_09: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_09 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_08: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_08 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_07: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_07 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_06: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_06 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_05: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_05 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_04: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_04 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_03: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_03 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_02: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_02 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_01: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_01 SW PAD Control Register

§SW_PAD_CTL_PAD_GPIO_00: RWRegister<u32>

SW_PAD_CTL_PAD_GPIO_00 SW PAD Control Register

§USB_OTG_ID_SELECT_INPUT: RWRegister<u32>

USB_OTG_ID_SELECT_INPUT DAISY Register

§FLEXPWM1_PWMA_SELECT_INPUT_0: RWRegister<u32>

FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register

§FLEXPWM1_PWMA_SELECT_INPUT_1: RWRegister<u32>

FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register

§FLEXPWM1_PWMA_SELECT_INPUT_2: RWRegister<u32>

FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register

§FLEXPWM1_PWMA_SELECT_INPUT_3: RWRegister<u32>

FLEXPWM1_PWMA_SELECT_INPUT_3 DAISY Register

§FLEXPWM1_PWMB_SELECT_INPUT_0: RWRegister<u32>

FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register

§FLEXPWM1_PWMB_SELECT_INPUT_1: RWRegister<u32>

FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register

§FLEXPWM1_PWMB_SELECT_INPUT_2: RWRegister<u32>

FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register

§FLEXPWM1_PWMB_SELECT_INPUT_3: RWRegister<u32>

FLEXPWM1_PWMB_SELECT_INPUT_3 DAISY Register

§FLEXSPI_DQS_FA_SELECT_INPUT: RWRegister<u32>

FLEXSPI_DQS_FA_SELECT_INPUT DAISY Register

§FLEXSPI_DQS_FB_SELECT_INPUT: RWRegister<u32>

FLEXSPI_DQS_FB_SELECT_INPUT DAISY Register

§KPP_COL_SELECT_INPUT_0: RWRegister<u32>

KPP_COL_SELECT_INPUT_0 DAISY Register

§KPP_COL_SELECT_INPUT_1: RWRegister<u32>

KPP_COL_SELECT_INPUT_1 DAISY Register

§KPP_COL_SELECT_INPUT_2: RWRegister<u32>

KPP_COL_SELECT_INPUT_2 DAISY Register

§KPP_COL_SELECT_INPUT_3: RWRegister<u32>

KPP_COL_SELECT_INPUT_3 DAISY Register

§KPP_ROW_SELECT_INPUT_0: RWRegister<u32>

KPP_ROW_SELECT_INPUT_0 DAISY Register

§KPP_ROW_SELECT_INPUT_1: RWRegister<u32>

KPP_ROW_SELECT_INPUT_1 DAISY Register

§KPP_ROW_SELECT_INPUT_2: RWRegister<u32>

KPP_ROW_SELECT_INPUT_2 DAISY Register

§KPP_ROW_SELECT_INPUT_3: RWRegister<u32>

KPP_ROW_SELECT_INPUT_3 DAISY Register

§LPI2C1_HREQ_SELECT_INPUT: RWRegister<u32>

LPI2C1_HREQ_SELECT_INPUT DAISY Register

§LPI2C1_SCL_SELECT_INPUT: RWRegister<u32>

LPI2C1_SCL_SELECT_INPUT DAISY Register

§LPI2C1_SDA_SELECT_INPUT: RWRegister<u32>

LPI2C1_SDA_SELECT_INPUT DAISY Register

§LPI2C2_SCL_SELECT_INPUT: RWRegister<u32>

LPI2C2_SCL_SELECT_INPUT DAISY Register

§LPI2C2_SDA_SELECT_INPUT: RWRegister<u32>

LPI2C2_SDA_SELECT_INPUT DAISY Register

§LPSPI1_PCS_SELECT_INPUT_0: RWRegister<u32>

LPSPI1_PCS_SELECT_INPUT_0 DAISY Register

§LPSPI1_SCK_SELECT_INPUT: RWRegister<u32>

LPSPI1_SCK_SELECT_INPUT DAISY Register

§LPSPI1_SDI_SELECT_INPUT: RWRegister<u32>

LPSPI1_SDI_SELECT_INPUT DAISY Register

§LPSPI1_SDO_SELECT_INPUT: RWRegister<u32>

LPSPI1_SDO_SELECT_INPUT DAISY Register

§LPSPI2_PCS_SELECT_INPUT_0: RWRegister<u32>

LPSPI2_PCS_SELECT_INPUT_0 DAISY Register

§LPSPI2_SCK_SELECT_INPUT: RWRegister<u32>

LPSPI2_SCK_SELECT_INPUT DAISY Register

§LPSPI2_SDI_SELECT_INPUT: RWRegister<u32>

LPSPI2_SDI_SELECT_INPUT DAISY Register

§LPSPI2_SDO_SELECT_INPUT: RWRegister<u32>

LPSPI2_SDO_SELECT_INPUT DAISY Register

§LPUART1_RXD_SELECT_INPUT: RWRegister<u32>

LPUART1_RXD_SELECT_INPUT DAISY Register

§LPUART1_TXD_SELECT_INPUT: RWRegister<u32>

LPUART1_TXD_SELECT_INPUT DAISY Register

§LPUART2_RXD_SELECT_INPUT: RWRegister<u32>

LPUART2_RXD_SELECT_INPUT DAISY Register

§LPUART2_TXD_SELECT_INPUT: RWRegister<u32>

LPUART2_TXD_SELECT_INPUT DAISY Register

§LPUART3_RXD_SELECT_INPUT: RWRegister<u32>

LPUART3_RXD_SELECT_INPUT DAISY Register

§LPUART3_TXD_SELECT_INPUT: RWRegister<u32>

LPUART3_TXD_SELECT_INPUT DAISY Register

§LPUART4_RXD_SELECT_INPUT: RWRegister<u32>

LPUART4_RXD_SELECT_INPUT DAISY Register

§LPUART4_TXD_SELECT_INPUT: RWRegister<u32>

LPUART4_TXD_SELECT_INPUT DAISY Register

§NMI_GLUE_NMI_SELECT_INPUT: RWRegister<u32>

NMI_GLUE_NMI_SELECT_INPUT DAISY Register

§SPDIF_IN1_SELECT_INPUT: RWRegister<u32>

SPDIF_IN1_SELECT_INPUT DAISY Register

§SPDIF_TX_CLK2_SELECT_INPUT: RWRegister<u32>

SPDIF_TX_CLK2_SELECT_INPUT DAISY Register

§USB_OTG_OC_SELECT_INPUT: RWRegister<u32>

USB_OTG_OC_SELECT_INPUT DAISY Register

§XEV_GLUE_RXEV_SELECT_INPUT: RWRegister<u32>

XEV_GLUE_RXEV_SELECT_INPUT DAISY Register

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

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where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.

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fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for T
where U: TryFrom<T>,

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type Error = >::Error

The type returned in the event of a conversion error.

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fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct imxrt_ral::iomuxc::RegisterBlock

Fields§

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct imxrt_ral::iomuxc::RegisterBlockCopy item path

Fields§

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct imxrt_ral::iomuxc::RegisterBlock

impl<T> Any for T
where T: 'static + ?Sized,

impl<T> Borrow<T> for T
where T: ?Sized,

impl<T> BorrowMut<T> for T
where T: ?Sized,

impl<T, U> Into<U> for T
where U: From<T>,

impl<T, U> TryFrom<U> for T
where U: Into<T>,

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,