Struct imxrt_ral::dma::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub CR: RWRegister<u32>,
    pub ES: RORegister<u32>,
    pub ERQ: RWRegister<u32>,
    pub EEI: RWRegister<u32>,
    pub CEEI: RWRegister<u8>,
    pub SEEI: RWRegister<u8>,
    pub CERQ: RWRegister<u8>,
    pub SERQ: RWRegister<u8>,
    pub CDNE: RWRegister<u8>,
    pub SSRT: RWRegister<u8>,
    pub CERR: RWRegister<u8>,
    pub CINT: RWRegister<u8>,
    pub INT: RWRegister<u32>,
    pub ERR: RWRegister<u32>,
    pub HRS: RORegister<u32>,
    pub EARS: RWRegister<u32>,
    pub DCHPRI3: RWRegister<u8>,
    pub DCHPRI2: RWRegister<u8>,
    pub DCHPRI1: RWRegister<u8>,
    pub DCHPRI0: RWRegister<u8>,
    pub DCHPRI7: RWRegister<u8>,
    pub DCHPRI6: RWRegister<u8>,
    pub DCHPRI5: RWRegister<u8>,
    pub DCHPRI4: RWRegister<u8>,
    pub DCHPRI11: RWRegister<u8>,
    pub DCHPRI10: RWRegister<u8>,
    pub DCHPRI9: RWRegister<u8>,
    pub DCHPRI8: RWRegister<u8>,
    pub DCHPRI15: RWRegister<u8>,
    pub DCHPRI14: RWRegister<u8>,
    pub DCHPRI13: RWRegister<u8>,
    pub DCHPRI12: RWRegister<u8>,
    pub TCD: [RegisterBlock; 16],
    /* private fields */
}

DMA

Fields

CR: RWRegister<u32>

Control Register

ES: RORegister<u32>

Error Status Register

ERQ: RWRegister<u32>

Enable Request Register

EEI: RWRegister<u32>

Enable Error Interrupt Register

CEEI: RWRegister<u8>

Clear Enable Error Interrupt Register

SEEI: RWRegister<u8>

Set Enable Error Interrupt Register

CERQ: RWRegister<u8>

Clear Enable Request Register

SERQ: RWRegister<u8>

Set Enable Request Register

CDNE: RWRegister<u8>

Clear DONE Status Bit Register

SSRT: RWRegister<u8>

Set START Bit Register

CERR: RWRegister<u8>

Clear Error Register

CINT: RWRegister<u8>

Clear Interrupt Request Register

INT: RWRegister<u32>

Interrupt Request Register

ERR: RWRegister<u32>

Error Register

HRS: RORegister<u32>

Hardware Request Status Register

EARS: RWRegister<u32>

Enable Asynchronous Request in Stop Register

DCHPRI3: RWRegister<u8>

Channel Priority Register

DCHPRI2: RWRegister<u8>

Channel Priority Register

DCHPRI1: RWRegister<u8>

Channel Priority Register

DCHPRI0: RWRegister<u8>

Channel Priority Register

DCHPRI7: RWRegister<u8>

Channel Priority Register

DCHPRI6: RWRegister<u8>

Channel Priority Register

DCHPRI5: RWRegister<u8>

Channel Priority Register

DCHPRI4: RWRegister<u8>

Channel Priority Register

DCHPRI11: RWRegister<u8>

Channel Priority Register

DCHPRI10: RWRegister<u8>

Channel Priority Register

DCHPRI9: RWRegister<u8>

Channel Priority Register

DCHPRI8: RWRegister<u8>

Channel Priority Register

DCHPRI15: RWRegister<u8>

Channel Priority Register

DCHPRI14: RWRegister<u8>

Channel Priority Register

DCHPRI13: RWRegister<u8>

Channel Priority Register

DCHPRI12: RWRegister<u8>

Channel Priority Register

TCD: [RegisterBlock; 16]

Cluster TCD%s, containing TCD*_SADDR, TCD*_SOFF, TCD*_ATTR, TCD*_NBYTES_MLNO, TCD*_NBYTES_MLOFFNO, TCD*_NBYTES_MLOFFYES, TCD*_SLAST, TCD*_DADDR, TCD*_DOFF, TCD*_CITER_ELINKNO, TCD*_CITER_ELINKYES, TCD*_DLASTSGA, TCD*_CSR, TCD*_BITER_ELINKNO, TCD*_BITER_ELINKYES