Struct imxrt_ral::dcp::RegisterBlock

source ·
#[repr(C)]
pub struct RegisterBlock {
Show 68 fields pub CTRL: RWRegister<u32>, pub CTRL_SET: RWRegister<u32>, pub CTRL_CLR: RWRegister<u32>, pub CTRL_TOG: RWRegister<u32>, pub STAT: RWRegister<u32>, pub STAT_SET: RWRegister<u32>, pub STAT_CLR: RWRegister<u32>, pub STAT_TOG: RWRegister<u32>, pub CHANNELCTRL: RWRegister<u32>, pub CHANNELCTRL_SET: RWRegister<u32>, pub CHANNELCTRL_CLR: RWRegister<u32>, pub CHANNELCTRL_TOG: RWRegister<u32>, pub CAPABILITY0: RWRegister<u32>, pub CAPABILITY1: RORegister<u32>, pub CONTEXT: RWRegister<u32>, pub KEY: RWRegister<u32>, pub KEYDATA: RWRegister<u32>, pub PACKET0: RORegister<u32>, pub PACKET1: RORegister<u32>, pub PACKET2: RORegister<u32>, pub PACKET3: RORegister<u32>, pub PACKET4: RORegister<u32>, pub PACKET5: RORegister<u32>, pub PACKET6: RORegister<u32>, pub CH0CMDPTR: RWRegister<u32>, pub CH0SEMA: RWRegister<u32>, pub CH0STAT: RWRegister<u32>, pub CH0STAT_SET: RWRegister<u32>, pub CH0STAT_CLR: RWRegister<u32>, pub CH0STAT_TOG: RWRegister<u32>, pub CH0OPTS: RWRegister<u32>, pub CH0OPTS_SET: RWRegister<u32>, pub CH0OPTS_CLR: RWRegister<u32>, pub CH0OPTS_TOG: RWRegister<u32>, pub CH1CMDPTR: RWRegister<u32>, pub CH1SEMA: RWRegister<u32>, pub CH1STAT: RWRegister<u32>, pub CH1STAT_SET: RWRegister<u32>, pub CH1STAT_CLR: RWRegister<u32>, pub CH1STAT_TOG: RWRegister<u32>, pub CH1OPTS: RWRegister<u32>, pub CH1OPTS_SET: RWRegister<u32>, pub CH1OPTS_CLR: RWRegister<u32>, pub CH1OPTS_TOG: RWRegister<u32>, pub CH2CMDPTR: RWRegister<u32>, pub CH2SEMA: RWRegister<u32>, pub CH2STAT: RWRegister<u32>, pub CH2STAT_SET: RWRegister<u32>, pub CH2STAT_CLR: RWRegister<u32>, pub CH2STAT_TOG: RWRegister<u32>, pub CH2OPTS: RWRegister<u32>, pub CH2OPTS_SET: RWRegister<u32>, pub CH2OPTS_CLR: RWRegister<u32>, pub CH2OPTS_TOG: RWRegister<u32>, pub CH3CMDPTR: RWRegister<u32>, pub CH3SEMA: RWRegister<u32>, pub CH3STAT: RWRegister<u32>, pub CH3STAT_SET: RWRegister<u32>, pub CH3STAT_CLR: RWRegister<u32>, pub CH3STAT_TOG: RWRegister<u32>, pub CH3OPTS: RWRegister<u32>, pub CH3OPTS_SET: RWRegister<u32>, pub CH3OPTS_CLR: RWRegister<u32>, pub CH3OPTS_TOG: RWRegister<u32>, pub DBGSELECT: RWRegister<u32>, pub DBGDATA: RORegister<u32>, pub PAGETABLE: RWRegister<u32>, pub VERSION: RORegister<u32>, /* private fields */
}
Expand description

DCP register reference index

Fields§

§CTRL: RWRegister<u32>

DCP control register 0

§CTRL_SET: RWRegister<u32>

DCP control register 0

§CTRL_CLR: RWRegister<u32>

DCP control register 0

§CTRL_TOG: RWRegister<u32>

DCP control register 0

§STAT: RWRegister<u32>

DCP status register

§STAT_SET: RWRegister<u32>

DCP status register

§STAT_CLR: RWRegister<u32>

DCP status register

§STAT_TOG: RWRegister<u32>

DCP status register

§CHANNELCTRL: RWRegister<u32>

DCP channel control register

§CHANNELCTRL_SET: RWRegister<u32>

DCP channel control register

§CHANNELCTRL_CLR: RWRegister<u32>

DCP channel control register

§CHANNELCTRL_TOG: RWRegister<u32>

DCP channel control register

§CAPABILITY0: RWRegister<u32>

DCP capability 0 register

§CAPABILITY1: RORegister<u32>

DCP capability 1 register

§CONTEXT: RWRegister<u32>

DCP context buffer pointer

§KEY: RWRegister<u32>

DCP key index

§KEYDATA: RWRegister<u32>

DCP key data

§PACKET0: RORegister<u32>

DCP work packet 0 status register

§PACKET1: RORegister<u32>

DCP work packet 1 status register

§PACKET2: RORegister<u32>

DCP work packet 2 status register

§PACKET3: RORegister<u32>

DCP work packet 3 status register

§PACKET4: RORegister<u32>

DCP work packet 4 status register

§PACKET5: RORegister<u32>

DCP work packet 5 status register

§PACKET6: RORegister<u32>

DCP work packet 6 status register

§CH0CMDPTR: RWRegister<u32>

DCP channel 0 command pointer address register

§CH0SEMA: RWRegister<u32>

DCP channel 0 semaphore register

§CH0STAT: RWRegister<u32>

DCP channel 0 status register

§CH0STAT_SET: RWRegister<u32>

DCP channel 0 status register

§CH0STAT_CLR: RWRegister<u32>

DCP channel 0 status register

§CH0STAT_TOG: RWRegister<u32>

DCP channel 0 status register

§CH0OPTS: RWRegister<u32>

DCP channel 0 options register

§CH0OPTS_SET: RWRegister<u32>

DCP channel 0 options register

§CH0OPTS_CLR: RWRegister<u32>

DCP channel 0 options register

§CH0OPTS_TOG: RWRegister<u32>

DCP channel 0 options register

§CH1CMDPTR: RWRegister<u32>

DCP channel 1 command pointer address register

§CH1SEMA: RWRegister<u32>

DCP channel 1 semaphore register

§CH1STAT: RWRegister<u32>

DCP channel 1 status register

§CH1STAT_SET: RWRegister<u32>

DCP channel 1 status register

§CH1STAT_CLR: RWRegister<u32>

DCP channel 1 status register

§CH1STAT_TOG: RWRegister<u32>

DCP channel 1 status register

§CH1OPTS: RWRegister<u32>

DCP channel 1 options register

§CH1OPTS_SET: RWRegister<u32>

DCP channel 1 options register

§CH1OPTS_CLR: RWRegister<u32>

DCP channel 1 options register

§CH1OPTS_TOG: RWRegister<u32>

DCP channel 1 options register

§CH2CMDPTR: RWRegister<u32>

DCP channel 2 command pointer address register

§CH2SEMA: RWRegister<u32>

DCP channel 2 semaphore register

§CH2STAT: RWRegister<u32>

DCP channel 2 status register

§CH2STAT_SET: RWRegister<u32>

DCP channel 2 status register

§CH2STAT_CLR: RWRegister<u32>

DCP channel 2 status register

§CH2STAT_TOG: RWRegister<u32>

DCP channel 2 status register

§CH2OPTS: RWRegister<u32>

DCP channel 2 options register

§CH2OPTS_SET: RWRegister<u32>

DCP channel 2 options register

§CH2OPTS_CLR: RWRegister<u32>

DCP channel 2 options register

§CH2OPTS_TOG: RWRegister<u32>

DCP channel 2 options register

§CH3CMDPTR: RWRegister<u32>

DCP channel 3 command pointer address register

§CH3SEMA: RWRegister<u32>

DCP channel 3 semaphore register

§CH3STAT: RWRegister<u32>

DCP channel 3 status register

§CH3STAT_SET: RWRegister<u32>

DCP channel 3 status register

§CH3STAT_CLR: RWRegister<u32>

DCP channel 3 status register

§CH3STAT_TOG: RWRegister<u32>

DCP channel 3 status register

§CH3OPTS: RWRegister<u32>

DCP channel 3 options register

§CH3OPTS_SET: RWRegister<u32>

DCP channel 3 options register

§CH3OPTS_CLR: RWRegister<u32>

DCP channel 3 options register

§CH3OPTS_TOG: RWRegister<u32>

DCP channel 3 options register

§DBGSELECT: RWRegister<u32>

DCP debug select register

§DBGDATA: RORegister<u32>

DCP debug data register

§PAGETABLE: RWRegister<u32>

DCP page table register

§VERSION: RORegister<u32>

DCP version register

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