Module CSCDR2

CCM Serial Clock Divider Register 2

Modules

LPI2C_CLK_PODF

Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

LPI2C_CLK_SEL

Selector for the LPI2C clock multiplexor