Module ctrl

Watchdog control
The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.
The watchdog can be triggered in software.

Structs

CTRL_SPEC

Watchdog control
The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.
The watchdog can be triggered in software.

Type Aliases

ENABLE_R

Field ENABLE reader - When not enabled the watchdog timer is paused

ENABLE_W

Field ENABLE writer - When not enabled the watchdog timer is paused

PAUSE_DBG0_R

Field PAUSE_DBG0 reader - Pause the watchdog timer when processor 0 is in debug mode

PAUSE_DBG0_W

Field PAUSE_DBG0 writer - Pause the watchdog timer when processor 0 is in debug mode

PAUSE_DBG1_R

Field PAUSE_DBG1 reader - Pause the watchdog timer when processor 1 is in debug mode

PAUSE_DBG1_W

Field PAUSE_DBG1 writer - Pause the watchdog timer when processor 1 is in debug mode

PAUSE_JTAG_R

Field PAUSE_JTAG reader - Pause the watchdog timer when JTAG is accessing the bus fabric

PAUSE_JTAG_W

Field PAUSE_JTAG writer - Pause the watchdog timer when JTAG is accessing the bus fabric

R

Register CTRL reader

TIME_R

Field TIME reader - Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered

TRIGGER_R

Field TRIGGER reader - Trigger a watchdog reset

TRIGGER_W

Field TRIGGER writer - Trigger a watchdog reset

W

Register CTRL writer