Module prim

Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2

Structs

PRIM_SPEC

Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2

Type Aliases

POSTDIV1_R

Field POSTDIV1 reader - divide by 1-7

POSTDIV1_W

Field POSTDIV1 writer - divide by 1-7

POSTDIV2_R

Field POSTDIV2 reader - divide by 1-7

POSTDIV2_W

Field POSTDIV2 writer - divide by 1-7

R

Register PRIM reader

W

Register PRIM writer