pub enum CMD_A {
WRITE = 0,
READ = 1,
}
Expand description
This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a ‘don’t care’ because writes to this register are not required. In slave-transmitter mode, a ‘0’ indicates that the data in IC_DATA_CMD is to be transmitted.
When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a ‘1’ is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
Reset value: 0x0
Value on reset: 0