Type Alias rp2040_pac::uart0::uartlcr_h::R
source · pub type R = R<UARTLCR_H_SPEC>;
Expand description
Register UARTLCR_H
reader
Aliased Type§
struct R { /* private fields */ }
Implementations§
source§impl R
impl R
sourcepub fn brk(&self) -> BRK_R
pub fn brk(&self) -> BRK_R
Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
sourcepub fn pen(&self) -> PEN_R
pub fn pen(&self) -> PEN_R
Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.
sourcepub fn eps(&self) -> EPS_R
pub fn eps(&self) -> EPS_R
Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.
sourcepub fn stp2(&self) -> STP2_R
pub fn stp2(&self) -> STP2_R
Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
sourcepub fn fen(&self) -> FEN_R
pub fn fen(&self) -> FEN_R
Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
sourcepub fn wlen(&self) -> WLEN_R
pub fn wlen(&self) -> WLEN_R
Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
sourcepub fn sps(&self) -> SPS_R
pub fn sps(&self) -> SPS_R
Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.