Type Alias rp2040_pac::pio0::ctrl::R

pub type R = R<CTRL_SPEC>;

Register CTRL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn sm_enable(&self) -> SM_ENABLE_R

Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.

pub fn sm_restart(&self) -> SM_RESTART_R

Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.

Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.

The program counter, the contents of the output shift register and the X/Y scratch registers are not affected.

pub fn clkdiv_restart(&self) -> CLKDIV_RESTART_R

Bits 8:11 - Restart a state machine’s clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.

Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines’ clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.

Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.