Struct rp2040_pac::dma::timer1::TIMER1_SPEC

pub struct TIMER1_SPEC;

Pacing (X/Y) Fractional Timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.

You can read this register and get timer1::R. You can reset, write, write_with_zero this register using timer1::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for TIMER1_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for TIMER1_SPEC

reset() method sets TIMER1 to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for TIMER1_SPEC

write(|w| ..) method takes timer1::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for TIMER1_SPEC

read() method returns timer1::R reader structure