Struct rp2040_pac::dma::ch::ch_trans_count::CH_TRANS_COUNT_SPEC

pub struct CH_TRANS_COUNT_SPEC;

DMA Channel 0 Transfer Count
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).

When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.

Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.

The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.

You can read this register and get ch_trans_count::R. You can reset, write, write_with_zero this register using ch_trans_count::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for CH_TRANS_COUNT_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CH_TRANS_COUNT_SPEC

reset() method sets CH_TRANS_COUNT to value 0

const RESET_VALUE: u32 = 0u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CH_TRANS_COUNT_SPEC

write(|w| ..) method takes ch_trans_count::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for CH_TRANS_COUNT_SPEC

read() method returns ch_trans_count::R reader structure