Module imxrt_ral::gpt::CR

GPT Control Register

Modules

• CLKSRC
  Clock Source select
• DBGEN
  GPT debug mode enable
• DOZEEN
  GPT Doze Mode Enable
• EN
  GPT Enable
• ENMOD
  GPT Enable mode
• EN_24M
  Enable 24 MHz clock input from crystal
• FO1
  See F03
• FO2
  See F03
• FO3
  FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register)
• FRR
  Free-Run or Restart mode
• IM1
  See IM2
• IM2
  IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event
• OM1
  See OM3
• OM2
  See OM3
• OM3
  OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode
• STOPEN
  GPT Stop Mode enable
• SWR
  Software reset
• WAITEN
  GPT Wait Mode enable