imxrt_
ral
0.5.3
In imxrt_
ral::
dma::
tcd::
TCD_
CSR::
BWC::
RW
Constant
imxrt_ral
::
dma
::
tcd
::
TCD_CSR
::
BWC
::
RW
::
BWC_2
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source
ยท
[
−
]
pub const BWC_2:
u16
= 0x02;
Expand description
eDMA engine stalls for 4 cycles after each R/W.