Module imxrt_ral::adc_etc::TRIG3_CTRL

ETC_TRIG Control Register

Modules

• CHAINX_DONE
  CHAINx done interrupt detection bit 0: CHAIN0 done interrupt bit 1: CHAIN1 done interrupt bit 2: CHAIN2 done interrupt bit 3: CHAIN3 done interrupt bit 4: CHAIN4 done interrupt bit 5: CHAIN5 done interrupt bit 6: CHAIN6 done interrupt bit 7: CHAIN7 done interrupt The done interrupts are cleared by writing a logic 1 to the bits
• SW_TRIG
  Software write 1 as the TRIGGER. This register is self-clearing.
• SYNC_MODE
  TRIG mode control . 1’b0: Disable sync mode; 1’b1: Enable sync mode
• TRIG_CHAIN
  TRIG chain length to the ADC. 0: Trig length is 1; … 7: Trig length is 8;
• TRIG_MODE
  TRIG mode register. 1’b0: hardware trigger. 1’b1: software trigger.
• TRIG_PRIORITY
  External trigger priority, 7 is highest, 0 is lowest .