Module imxrt_ral::adc_etc::CTRL

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ADC_ETC Global Control Register

Modules§

  • DMA_MODE_SEL
    1’b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared
  • EXT0_TRIG_ENABLE
    TSC0 TRIG enable register. 1’b1: enable external TSC0 trigger. 1’b0: disable external TSC0 trigger.
  • EXT0_TRIG_PRIORITY
    External TSC0 trigger priority, 7 is Highest, 0 is lowest .
  • EXT1_TRIG_ENABLE
    TSC1 TRIG enable register. 1’b1: enable external TSC1 trigger. 1’b0: disable external TSC1 trigger.
  • EXT1_TRIG_PRIORITY
    External TSC1 trigger priority, 7 is Highest, 0 is lowest .
  • PRE_DIVIDER
    Pre-divider for trig delay and interval .
  • SOFTRST
    Software reset, high active. When write 1 ,all logical will be reset.
  • TRIG_ENABLE
    TRIG enable register
  • TSC_BYPASS
    1’b1: TSC is bypassed to ADC2. 1’b0: TSC not bypassed. To use ADC2, this bit should be cleared.