Module CFG

Source
Expand description

Configuration register

Modules§

ADHSC
High Speed Configuration
ADICLK
Input Clock Select
ADIV
Clock Divide Select
ADLPC
Low-Power Configuration
ADLSMP
Long Sample Time Configuration
ADSTS
Defines the sample time duration
ADTRG
Conversion Trigger Select
AVGS
Hardware Average select
MODE
Conversion Mode Selection
OVWREN
Data Overwrite Enable
REFSEL
Voltage Reference Selection