Struct cortex_m::peripheral::scb::RegisterBlock

source ·
#[repr(C)]
pub struct RegisterBlock {
Show 14 fields pub icsr: RW<u32>, pub vtor: RW<u32>, pub aircr: RW<u32>, pub scr: RW<u32>, pub ccr: RW<u32>, pub shpr: [RW<u8>; 12], pub shcsr: RW<u32>, pub cfsr: RW<u32>, pub hfsr: RW<u32>, pub dfsr: RW<u32>, pub mmfar: RW<u32>, pub bfar: RW<u32>, pub afsr: RW<u32>, pub cpacr: RW<u32>, /* private fields */
}
Expand description

Register block

Fields§

§icsr: RW<u32>

Interrupt Control and State

§vtor: RW<u32>

Vector Table Offset (not present on Cortex-M0 variants)

§aircr: RW<u32>

Application Interrupt and Reset Control

§scr: RW<u32>

System Control

§ccr: RW<u32>

Configuration and Control

§shpr: [RW<u8>; 12]

System Handler Priority (word accessible only on Cortex-M0 variants)

On ARMv7-M, shpr[0] points to SHPR1

On ARMv6-M, shpr[0] points to SHPR2

§shcsr: RW<u32>

System Handler Control and State

§cfsr: RW<u32>

Configurable Fault Status (not present on Cortex-M0 variants)

§hfsr: RW<u32>

HardFault Status (not present on Cortex-M0 variants)

§dfsr: RW<u32>

Debug Fault Status (not present on Cortex-M0 variants)

§mmfar: RW<u32>

MemManage Fault Address (not present on Cortex-M0 variants)

§bfar: RW<u32>

BusFault Address (not present on Cortex-M0 variants)

§afsr: RW<u32>

Auxiliary Fault Status (not present on Cortex-M0 variants)

§cpacr: RW<u32>

Coprocessor Access Control (not present on Cortex-M0 variants)

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