Struct cortex_m::peripheral::nvic::RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { pub iser: [RW<u32>; 16], pub icer: [RW<u32>; 16], pub ispr: [RW<u32>; 16], pub icpr: [RW<u32>; 16], pub iabr: [RO<u32>; 16], pub ipr: [RW<u8>; 496], pub stir: WO<u32>, /* private fields */ }
Expand description

Register block

Fields§

§iser: [RW<u32>; 16]

Interrupt Set-Enable

§icer: [RW<u32>; 16]

Interrupt Clear-Enable

§ispr: [RW<u32>; 16]

Interrupt Set-Pending

§icpr: [RW<u32>; 16]

Interrupt Clear-Pending

§iabr: [RO<u32>; 16]

Interrupt Active Bit (not present on Cortex-M0 variants)

§ipr: [RW<u8>; 496]

Interrupt Priority

On ARMv7-M, 124 word-sized registers are available. Each of those contains of 4 interrupt priorities of 8 byte each.The architecture specifically allows accessing those along byte boundaries, so they are represented as 496 byte-sized registers, for convenience, and to allow atomic priority updates.

On ARMv6-M, the registers must only be accessed along word boundaries, so convenient byte-sized representation wouldn’t work on that architecture.

§stir: WO<u32>

Software Trigger Interrupt

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