Module regs

Structs

DmaccarxBr

Channel current application receive buffer register

DmaccarxDr

Channel current application receive descriptor register

DmaccatxBr

Channel current application transmit buffer register

DmaccatxDr

Channel current application transmit descriptor register

Dmaccr

Channel control register

Dmacier

Channel interrupt enable register

Dmacmfcr

Channel missed frame count register

DmacrxCr

Channel receive control register

DmacrxDlar

Channel Rx descriptor list address register

DmacrxDtpr

Channel Rx descriptor tail pointer register

DmacrxIwtr

Channel Rx interrupt watchdog timer register

DmacrxRlr

Channel Rx descriptor ring length register

Dmacsr

Channel status register

DmactxCr

Channel transmit control register

DmactxDlar

Channel Tx descriptor list address register

DmactxDtpr

Channel Tx descriptor tail pointer register

DmactxRlr

Channel Tx descriptor ring length register

Dmadsr

Debug status register

Dmaisr

Interrupt status register

Dmamr

DMA mode register

Dmasbmr

System bus mode register

Mac1ustcr

1-microsecond-tick counter register

Maca0hr

Address 0 high register

Maca0lr

Address 0 low register

Macacr

Auxiliary control register

Macahr

Address 1/2/3 high register

Macalr

Address 1/2/3 low register

Macarpar

ARP address register

Macatsnr

Auxiliary timestamp nanoseconds register

Macatssr

Auxiliary timestamp seconds register

Maccr

Operating mode configuration register

Macdr

Debug register

Macecr

Extended operating mode configuration register

Machtr

Hash Table 0/1 register

Machwf1r

HW feature 1 register

Machwf2r

HW feature 2 register

Macier

Interrupt enable register

Macisr

Interrupt status register

Macivir

Inner VLAN inclusion register

Macl3a00r

MACL3A00R

Macl3a01r

Layer3 address 0 filter 1 Register

Macl3a20

Layer3 Address 2 filter 0 register

Macl3a30

Layer3 Address 3 filter 0 register

Macl3a10r

Layer3 address 1 filter 0 register

Macl3a11r

Layer3 address 1 filter 1 register

Macl3a21r

Layer3 address 2 filter 1 Register

Macl3a31r

Layer3 address 3 filter 1 register

Macl3l4c0r

L3 and L4 control 0 register

Macl3l4c1r

L3 and L4 control 1 register

Macl4a0r

Layer4 address filter 0 register

Macl4a1r

Layer 4 address filter 1 register

Maclcsr

LPI control status register

Macletr

LPI entry timer register

Maclmir

Log message interval register

Macltcr

LPI timers control register

Macmdioar

MDIO address register

Macmdiodr

MDIO data register

Macpcsr

PMT control status register

Macpfr

Packet filtering control register

Macpocr

PTP Offload control register

Macppscr

PPS control register

Macppsir

PPS interval register

Macppsttnr

PPS target time nanoseconds register

Macppsttsr

PPS target time seconds register

Macppswr

PPS width register

MacqtxFcr

Tx Queue flow control register

Macrwkpfr

Remove wakeup packet filter register

MacrxFcr

Rx flow control register

MacrxTxSr

Rx Tx status register

Macspi0r

PTP Source Port Identity 0 Register

Macspi1r

PTP Source port identity 1 register

Macspi2r

PTP Source port identity 2 register

Macssir

Sub-second increment register

Macstnr

System time nanoseconds register

Macstnur

System time nanoseconds update register

Macstsr

System time seconds register

Macstsur

System time seconds update register

Mactsar

Timestamp addend register

Mactscr

Timestamp control Register

Mactseacr

Timestamp Egress asymmetric correction register

Mactsecnr

Timestamp Egress correction nanosecond register

Mactsiacr

Timestamp Ingress asymmetric correction register

Mactsicnr

Timestamp Ingress correction nanosecond register

Mactssr

Timestamp status register

MactxTssnr

Tx timestamp status nanoseconds register

MactxTsssr

Tx timestamp status seconds register

Macvhtr

VLAN Hash table register

Macvir

VLAN inclusion register

Macvr

Version register

Macvtr

VLAN tag register

Macwtr

Watchdog timeout register

MmcControl

MMC control register

MmcRxInterrupt

MMC Rx interrupt register

MmcRxInterruptMask

MMC Rx interrupt mask register

MmcTxInterrupt

MMC Tx interrupt register

MmcTxInterruptMask

MMC Tx interrupt mask register

Mtlisr

Interrupt status Register

Mtlomr

Operating mode Register

Mtlqicsr

Queue interrupt control status Register

MtlrxQdr

Rx queue debug register

MtlrxQmpocr

Rx queue missed packet and overflow counter register

MtlrxQomr

Rx queue operating mode register

MtltxQdr

Tx queue debug Register

MtltxQomr

Tx queue operating mode Register

MtltxQur

Tx queue underflow register

RxAlignmentErrorPackets

Rx alignment error packets register

RxCrcErrorPackets

Rx CRC error packets register

RxLpiTranCntr

Rx LPI transition counter register

RxLpiUsecCntr

Rx LPI microsecond counter register

RxUnicastPacketsGood

Rx unicast packets good register

TxLpiTranCntr

Tx LPI transition counter register

TxLpiUsecCntr

Tx LPI microsecond timer register

TxMultipleCollisionGoodPackets

Tx multiple collision good packets register

TxPacketCountGood

Tx packet count good register

TxSingleCollisionGoodPackets

Tx single collision good packets register