Module uartdr

Data Register, UARTDR

Structs

UARTDR_SPEC

Data Register, UARTDR

Type Aliases

BE_R

Field BE reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.

DATA_R

Field DATA reader - Receive (read) data character. Transmit (write) data character.

DATA_W

Field DATA writer - Receive (read) data character. Transmit (write) data character.

FE_R

Field FE reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.

OE_R

Field OE reader - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.

PE_R

Field PE reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.

R

Register UARTDR reader

W

Register UARTDR writer