Module ch_ctrl_trig

DMA Channel 0 Control and Status

Structs

CH_CTRL_TRIG_SPEC

DMA Channel 0 Control and Status

Enums

DATA_SIZE_A

Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

RING_SIZE_A

Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

TREQ_SEL_A

Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ

Type Aliases

AHB_ERROR_R

Field AHB_ERROR reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.

BSWAP_R

Field BSWAP reader - Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

BSWAP_W

Field BSWAP writer - Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.

BUSY_R

Field BUSY reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.

CHAIN_TO_R

Field CHAIN_TO reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).
Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour.

CHAIN_TO_W

Field CHAIN_TO writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = (this channel).
Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour.

DATA_SIZE_R

Field DATA_SIZE reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

DATA_SIZE_W

Field DATA_SIZE writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.

EN_R

Field EN reader - DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

EN_W

Field EN writer - DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)

HIGH_PRIORITY_R

Field HIGH_PRIORITY reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

HIGH_PRIORITY_W

Field HIGH_PRIORITY writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.

INCR_READ_R

Field INCR_READ reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

INCR_READ_W

Field INCR_READ writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.

INCR_WRITE_R

Field INCR_WRITE reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

INCR_WRITE_W

Field INCR_WRITE writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.

IRQ_QUIET_R

Field IRQ_QUIET reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

IRQ_QUIET_W

Field IRQ_QUIET writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.

R

Register CH_CTRL_TRIG reader

READ_ERROR_R

Field READ_ERROR reader - If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

READ_ERROR_W

Field READ_ERROR writer - If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)

RING_SEL_R

Field RING_SEL reader - Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

RING_SEL_W

Field RING_SEL writer - Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.

RING_SIZE_R

Field RING_SIZE reader - Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

RING_SIZE_W

Field RING_SIZE writer - Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.

SNIFF_EN_R

Field SNIFF_EN reader - If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

SNIFF_EN_W

Field SNIFF_EN writer - If 1, this channel’s data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.

TREQ_SEL_R

Field TREQ_SEL reader - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ

TREQ_SEL_W

Field TREQ_SEL writer - Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ

W

Register CH_CTRL_TRIG writer

WRITE_ERROR_R

Field WRITE_ERROR reader - If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)

WRITE_ERROR_W

Field WRITE_ERROR writer - If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)