Module regs

Structs

Ahb1enr

RCC AHB1 Clock Register

Ahb1lpenr

RCC AHB1 Sleep Clock Register

Ahb1rstr

RCC AHB1 Peripheral Reset Register

Ahb2enr

RCC AHB2 Clock Register

Ahb2lpenr

RCC AHB2 Sleep Clock Register

Ahb2rstr

RCC AHB2 Peripheral Reset Register

Ahb3enr

RCC AHB3 Clock Register

Ahb3lpenr

RCC AHB3 Sleep Clock Register

Ahb3rstr

RCC AHB3 Reset Register

Ahb4enr

RCC AHB4 Clock Register

Ahb4lpenr

RCC AHB4 Sleep Clock Register

Ahb4rstr

RCC AHB4 Peripheral Reset Register

Apb1henr

RCC APB1 Clock Register

Apb1hlpenr

RCC APB1 High Sleep Clock Register

Apb1hrstr

RCC APB1 Peripheral Reset Register

Apb1lenr

RCC APB1 Clock Register

Apb1llpenr

RCC APB1 Low Sleep Clock Register

Apb1lrstr

RCC APB1 Peripheral Reset Register

Apb2enr

RCC APB2 Clock Register

Apb2lpenr

RCC APB2 Sleep Clock Register

Apb2rstr

RCC APB2 Peripheral Reset Register

Apb3enr

RCC APB3 Clock Register

Apb3lpenr

RCC APB3 Sleep Clock Register

Apb3rstr

RCC APB3 Peripheral Reset Register

Apb4enr

RCC APB4 Clock Register

Apb4lpenr

RCC APB4 Sleep Clock Register

Apb4rstr

RCC APB4 Peripheral Reset Register

Bdcr

RCC Backup Domain Control Register

C1Ahb1enr

RCC AHB1 Clock Register

C1Ahb1lpenr

RCC AHB1 Sleep Clock Register

C1Ahb2enr

RCC AHB2 Clock Register

C1Ahb2lpenr

RCC AHB2 Sleep Clock Register

C1Ahb3enr

RCC AHB3 Clock Register

C1Ahb3lpenr

RCC AHB3 Sleep Clock Register

C1Ahb4enr

RCC AHB4 Clock Register

C1Ahb4lpenr

RCC AHB4 Sleep Clock Register

C1Apb1henr

RCC APB1 Clock Register

C1Apb1hlpenr

RCC APB1 High Sleep Clock Register

C1Apb1lenr

RCC APB1 Clock Register

C1Apb1llpenr

RCC APB1 Low Sleep Clock Register

C1Apb2enr

RCC APB2 Clock Register

C1Apb2lpenr

RCC APB2 Sleep Clock Register

C1Apb3enr

RCC APB3 Clock Register

C1Apb3lpenr

RCC APB3 Sleep Clock Register

C1Apb4enr

RCC APB4 Clock Register

C1Apb4lpenr

RCC APB4 Sleep Clock Register

C1Rsr

RCC Reset Status Register

Cfgr

RCC Clock Configuration Register

Cicr

RCC Clock Source Interrupt Clear Register

Cier

RCC Clock Source Interrupt Enable Register

Cifr

RCC Clock Source Interrupt Flag Register

Cr

clock control register

Crrcr

RCC Clock Recovery RC Register

Csicfgr

RCC CSI configuration register

Csr

RCC Clock Control and Status Register

D1ccipr

RCC Domain 1 Kernel Clock Configuration Register

D1cfgr

RCC Domain 1 Clock Configuration Register

D2ccip1r

RCC Domain 2 Kernel Clock Configuration Register

D2ccip2r

RCC Domain 2 Kernel Clock Configuration Register

D2cfgr

RCC Domain 2 Clock Configuration Register

D3amr

RCC D3 Autonomous mode Register

D3ccipr

RCC Domain 3 Kernel Clock Configuration Register

D3cfgr

RCC Domain 3 Clock Configuration Register

Gcr

Global Control Register

Hsicfgr

RCC HSI configuration register

Icscr

RCC Internal Clock Source Calibration Register

Pllcfgr

RCC PLLs Configuration Register

Pllckselr

RCC PLLs Clock Source Selection Register

Plldivr

RCC PLL1 Dividers Configuration Register

Pllfracr

RCC PLL Fractional Divider Register

Rsr

RCC Reset Status Register